High-Performance and Energy-Area Efficient Approximate Full Adder for Error Tolerant Applications

In this paper, a novel approximate Full Adder cell is presented which is based on the combination of standard CMOS logic (S-CMOS) and pass transistor logic (PTL) styles. The carbon nanotube field-effect transistor (CNFET) technology is used to simulate and implement the proposed cell. Comprehensive simulations at various power supplies, output loads, and ambient temperatures are conducted using the HSPICE tool. According to simulation results, its delay, power-delay product (PDP), energy-delay product (EDP), and normalized energy-delay-area product (NEDAP) improve by 18%, 10%, 39%, and 15% compared with the best existing design. The effects of diameter variations of carbon nanotubes (CNTs) on the functionality of the circuits are studied by Monte Carlo (MC) transient analysis. Simulation results confirm that the proposed cell is resistant to the process variations. At the application level, all circuits are employed in image blending to assess their efficacy in terms of peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) index criteria using the MATLAB tool.