Lv11
28 积分 2024-06-12 加入
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator
3小时前
已完结
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
3小时前
已完结
A 3.84 GHz 32 fs RMS Jitter Over-Sampling PLL with High-Gain Cross-Switching Phase Detector
3小时前
已关闭
Glitch-Free NAND-Based Digitally Controlled Delay-Lines
20天前
已完结
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
3个月前
已完结
Novel Circuit Architecture for configurable eDP and MIPI DPHY IO
3个月前
已完结
A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2
3个月前
已完结
A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-$\mu{\rm m}$ CMOS
3个月前
已完结
Nested Miller compensation in low-power CMOS design
3个月前
已完结
A low-voltage, low quiescent current, low drop-out regulator
4个月前
已完结
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