Lv2
120 积分 2024-01-15 加入
Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique
1个月前
已完结
A 4×50Gb/s NRZ 1.5pJ/b Co-Packaged and Fiber-Terminated 4-Channel Optical RX
1个月前
已完结
Analysis of the Bridged T-Coil Circuit Using the Extra-Element Theorem
3个月前
已完结
A 1cnm 14.4Gb/s/pin 16Gb LPDDR6 SDRAM with Efficiency Mode, LDO-Based WCK Tree, Dynamic Write NT-ODT, Fast CS Control and System Meta Mode
4个月前
已完结
A 32Gb/s/lane 0.83Tb/s/mm UCIe Compliant Die-to-Die Link Over 25mm Standard Package
5个月前
已完结
Bandwidth Extension
6个月前
已完结
A 0.2–2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer
7个月前
已完结
A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology
7个月前
已完结
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer
7个月前
已完结
A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization
7个月前
已完结
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