Lv2
110 积分 2024-01-15 加入
A 1cnm 14.4Gb/s/pin 16Gb LPDDR6 SDRAM with Efficiency Mode, LDO-Based WCK Tree, Dynamic Write NT-ODT, Fast CS Control and System Meta Mode
14天前
已完结
A 32Gb/s/lane 0.83Tb/s/mm UCIe Compliant Die-to-Die Link Over 25mm Standard Package
1个月前
已完结
Bandwidth Extension
2个月前
已完结
A 0.2–2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer
3个月前
已完结
A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology
3个月前
已完结
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer
3个月前
已完结
A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization
3个月前
已完结
23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs
3个月前
已完结
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS
3个月前
已完结
A 11.4-Gbps/lane MIPI 32-bit C-PHY and D-PHY combo transmitter with 3-tap FFE
3个月前
已完结
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