Lv4
575 积分 2020-08-17 加入
A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring
14天前
已完结
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
14天前
已完结
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques
14天前
已完结
A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring
14天前
已完结
A 0.29pJ/b 5.27Tb/s/mm UCIe Advanced Package Link in 3nm FinFET with 2.5D CoWoS Packaging
14天前
已完结
A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating
14天前
已完结
8.2 A 32Gb/s 12.35Tb/s/mm 2 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging
16天前
已完结
GaN Chiplet Technology Based on 300mm GaN-on-Silicon
23天前
已完结
SHINSAI: A 586 mm 2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory
24天前
已完结
8.2 A 32Gb/s 12.35Tb/s/mm 2 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging
1个月前
已完结
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