Lv52
1090 积分 2022-04-27 加入
8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS
5天前
已完结
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects
8天前
已完结
A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS
8天前
已完结
Capacitively-Coupled CMOS VCSEL Driver Circuits
13天前
已完结
Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-f/sub T/ SiGe process
1个月前
已完结
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET
2个月前
已完结
A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS
3个月前
已完结
4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS
3个月前
已完结
An Analysis of Current-mode Drivers in 40-nm CMOS Technology
3个月前
已完结
Matching properties of MOS transistors
3个月前
已完结