Lv11
60 积分 2024-08-19 加入
Methodology for automated layout migration for 90nm Itanium/spl reg/2 processor design
7小时前
待确认
TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework
2个月前
已完结
Echelon: a multilayer detailed area router
2个月前
已完结
A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
2个月前
已完结
CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement
2个月前
已完结
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes
3个月前
已完结
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map
3个月前
已完结
Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources
3个月前
已完结
A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides
5个月前
已完结
Algorithms and data structures for fast and good VLSI routing
8个月前
已完结
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