Lv2
116 积分 2020-12-14 加入
A 130–160 GHz Frequency Doubler with Fully Transformer-Based Networks in 40nm Bulk CMOS
1个月前
已完结
A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver
1个月前
已完结
Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS
1个月前
已完结
Asynchronous vs Synchronous SAR ADCs – Performance Beyond Nominal Speed
3个月前
已完结
A 50 Gb/s PAM-4 Receiver Featuring Current-Reuse AFE and Single-Loop Half-Rate Reference-Less Bang-Bang CDR in 40-nm CMOS
4个月前
已完结
A 4 × 224 Gb/s Single-Ended PAM-4 Transceiver Front-End With Noise Suppression Technique and Cascaded Equalizers in 130-nm SiGe BiCMOS
4个月前
已完结
A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O
5个月前
已完结
A 112Gb/s Analog-MUX-based PAM-4 Transmitter with Inherent 2-tap FFE in 65nm CMOS
5个月前
已完结
A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology
5个月前
已完结
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS
5个月前
已完结
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