Lv2
120 积分 2020-12-14 加入
A 50 Gb/s PAM-4 Receiver Featuring Current-Reuse AFE and Single-Loop Half-Rate Reference-Less Bang-Bang CDR in 40-nm CMOS
2天前
已完结
A 4 × 224 Gb/s Single-Ended PAM-4 Transceiver Front-End With Noise Suppression Technique and Cascaded Equalizers in 130-nm SiGe BiCMOS
2天前
已完结
A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O
26天前
已完结
A 112Gb/s Analog-MUX-based PAM-4 Transmitter with Inherent 2-tap FFE in 65nm CMOS
26天前
已完结
A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology
27天前
已完结
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS
27天前
已完结
A 0.0035-mm2 0.42-pJ/bit 8–32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE
28天前
已完结
A 28-nm 8–28-GHz Eight-Phase Clock Generator Using an Injection-Locked Dual-Feedback Ring Oscillator
28天前
已完结
A 56-GHz Fractional-N PLL With 110-fs Jitter
28天前
已完结
A 0.0006-mm2 0.13-pJ/bit 9–21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1:3 DEMUX in 65-nm CMOS
29天前
已完结
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