Lv2
198 积分 2024-02-27 加入
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology
1个月前
已完结
内嵌电源管理的实时时钟芯片的研究与设计
2个月前
已完结
Ultra-Low-Power High PSRR Sub-1 V Voltage Reference Circuit in 22 nm FDSOI CMOS
3个月前
已完结
A 2 A Dual Loop LDO With Dynamic Negative Feedback Loop and Gm Boosting Error Amplifier for Off-Chip and Cap-Less Applications
4个月前
已完结
A 1.48-fs FoM Analog Capacitorless-LDO With Cascade-Inverter-Based Pseudo-Power Transistor
4个月前
已完结
A 0.5–1-V Time-Voltage Hybrid Domain Dual- Loop Analog LDO With Wide-Bandwidth High PSR in 28 nm
4个月前
已完结
A 0.35mm2 94.25μ W Fully Integrated NFC Tag IC Using 0.13μ m CMOS Process
4个月前
已完结
A 54-nA Quiescent Current Capless LDO With −39-dB PSRR at 1 MHz Using a Load-Tracking Bandwidth Extension Technique
4个月前
已完结
An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient
6个月前
已完结
A Fully Integrated, Domino-Like-Buffered LDO Regulator With High Power-Supply Rejection Across the Full Frequency Spectrum
6个月前
已完结
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