Lv7
4985 积分 2020-12-25 加入
A 1cnm 14.4Gb/s/pin 16Gb LPDDR6 SDRAM with Efficiency Mode, LDO-Based WCK Tree, Dynamic Write NT-ODT, Fast CS Control and System Meta Mode
2个月前
已完结
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS
3个月前
已完结
Robust Tracking for the Open-Loop Unstable Process with Time Delay by Combining PID type-p and Inner Compensators
3个月前
已完结
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology
4个月前
已完结
A 0.87pJ/b 17Gb/s/pin Parallel Receiver with a Local DQS Recovery for a Supply-Noise-Tolerant DQS Distribution in High-Performance NAND Flash Interfaces
4个月前
已完结
TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory Interface
4个月前
已完结
A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications
5个月前
已完结
A Fast-Lock DLL with Prediction-Based Fast-Track FDL Structure for DDR5 SDRAMs
5个月前
已关闭
A Novel High Speed 2-Step TDC-Based All-Digital DLL for DDR SDRAM Applications
5个月前
已完结
28.7 A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL
5个月前
已完结
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