Lv6
2350 积分 2022-06-22 加入
Analog designer
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS
15天前
已完结
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS
15天前
已完结
Time-Domain Versus Voltage-Domain Data Conversion: Principles, opportunities, and challenges
16天前
已完结
Design Techniques for Wideband CMOS Power Amplifiers for Wireless Communications
1个月前
已完结
An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz
2个月前
已完结
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
4个月前
已完结
Cell-based fully integrated CMOS frequency synthesizers
4个月前
已完结
Cell-based fully integrated CMOS frequency synthesizers
4个月前
已完结
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS
5个月前
已完结
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
5个月前
已完结
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