Lv6
2300 积分 2022-06-22 加入
Analog designer
Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview
13天前
已完结
Performance Bounds of ADC-Based Receivers Due to Clock Jitter
29天前
已完结
An 800GbE PAM-4 PHY Transceiver for 42dB Copper and Direct-Drive Optical Applications in 7nm
29天前
已完结
A 28-nm 8–28-GHz Eight-Phase Clock Generator Using an Injection-Locked Dual-Feedback Ring Oscillator
30天前
已完结
An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm
30天前
已完结
A Class-F CMOS Oscillator
1个月前
已完结
A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology
1个月前
已关闭
A 10 GHz low-power multi-modulus frequency divider using Extended True Single-Phase Clock (E-TSPC) Logic
1个月前
已完结
A Family of LowPower Truly Modular Programmable Dividers in Standard 0.35m CMOS Technology
1个月前
已完结
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET
1个月前
已完结
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