Lv6
2380 积分 2022-06-22 加入
Analog designer
A 31.5–36-GHz Low-Spur Digitally Assisted Gain-Boosting Charge-Sharing Locking PLL Achieving 54-fs RMS Jitter
16天前
已关闭
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology
1个月前
已完结
A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation
2个月前
已完结
Phase Noise Integration Limits for Jitter Estimation in Wireline Transmitters
2个月前
已完结
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS
3个月前
已完结
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS
3个月前
已完结
Time-Domain Versus Voltage-Domain Data Conversion: Principles, opportunities, and challenges
3个月前
已完结
Design Techniques for Wideband CMOS Power Amplifiers for Wireless Communications
4个月前
已完结
An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz
5个月前
已完结
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
7个月前
已完结
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