Lv62
2160 积分 2022-06-22 加入
Analog designer
A 10 GHz low-power multi-modulus frequency divider using Extended True Single-Phase Clock (E-TSPC) Logic
1天前
已完结
A Family of LowPower Truly Modular Programmable Dividers in Standard 0.35m CMOS Technology
1天前
已完结
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET
3天前
已完结
A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology
5天前
已完结
Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)
5天前
已完结
A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology
5天前
已完结
A fractional-N frequency synthesizer with phase synchronization and programmable phase control capability
5天前
已完结
A 27.2–31.2 GHz 92-fs rms Integrated Jitter, Fractional-N Subsampling PLL Using Phase Rotating Technique in 65-nm CMOS
5天前
已完结
A 951-fs rms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator
5天前
已完结
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration
1个月前
已完结
皖公网安备34019202002308
