Lv6
2020 积分 2022-06-22 加入
Analog designer
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, −258.7-dB FOM, and −75.17-dBc Reference Spur
8天前
已完结
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector
8天前
已完结
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS
21天前
已关闭
A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology
3个月前
已完结
Design Techniques for High-Speed Wireline Transmitters
3个月前
已完结
Design and Optimization of T-Coil-Enhanced ESD Circuit with Upsampling Convolutional Neural Network
3个月前
已完结
A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators
3个月前
已完结
A Mm-Wave 5G Broadband Power Amplifier with Subthreshold Adaptive Biasing Network in 22 nm FD-SOI CMOS
4个月前
已完结
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement
4个月前
已完结
A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-$N$ Digital PLLs
4个月前
已完结
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