Lv5
970 积分 2026-04-03 加入
Area minimization algorithm for parallel prefix adders under bitwise delay constraints
5小时前
待确认
Accelerating tensor multiplication by exploring hybrid product with hardware and software co-design
3天前
待确认
Low-Power Multiplier Designs by Leveraging Correlations of 2$\times$×2 Encoded Partial Products
1个月前
已完结
Minimization of switching activities of partial products for designing low-power multipliers
1个月前
已完结
Bit-Separable Radix-4 Booth Multiplier for Power-Efficient CNN Accelerator
2个月前
已完结
Streamlined Tree Computation Framework for 32-Bit Parallel Prefix Adders
2个月前
已完结
Size-Optimized Depth-Constrained Large Parallel Prefix Circuits
2个月前
已完结
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs
2个月前
已完结
High Energy Efficiency Radix-4 Booth Multiplier with Zero Encoding Skipping Mechanism
2个月前
已完结
Implementation of 32-bit Ling and Jackson adders
2个月前
已完结
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