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20 积分 2023-07-24 加入
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS
50分钟前
待确认
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology
28天前
已完结
2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS
28天前
已完结
Multiple Edge Responses for Fast and Accurate System Simulations
5个月前
已完结
A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application
6个月前
已完结
The Design of a Phase Interpolator [The Analog Mind]
7个月前
已完结
A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application
1年前
已完结
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