Lv5
1187 积分 2024-01-28 加入
Design of DRAM sense amplifier using 45nm technology
1个月前
已完结
GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process
2个月前
已完结
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process
2个月前
已完结
对5G SOC基带芯片LPDDR4X的SIPI设计与分析
2个月前
已关闭
On-Die Decoupling Capacitor Optimization for DDR IO Interface
2个月前
已完结
28.7 A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL
2个月前
已完结
Study and Analysis of Leakage current and leakage power in 1T1C DRAM at Nano Scale Technology
2个月前
已完结
Novel High Density 3D Buffer Memory Enabled by IGZO Channel Charge Coupled Device
3个月前
已完结
A system level optimization of on-chip thermoelectric cooling via Taguchi-Grey method
4个月前
已关闭
Work Function Engineering to Improve Data Retention Due to Floating Body in 3-D GAA Stacked Nanosheet Based DRAM
5个月前
已完结
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