Lv6
2330 积分 2025-06-16 加入
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization
26天前
已完结
1- and 80-MS/s SAR ADCs in 40-nm CMOS With End-to-End Compilation
26天前
已完结
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design
27天前
已完结
Input Referred Comparator Noise in SAR ADCs
5个月前
已完结
Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures
5个月前
已完结
A 12bit 16MS/s Asynchronous SAR ADC with Speed-Enhanced Comparator and TSPC Latch
6个月前
已完结
A 0.5-0.8V 10-85 MS/s 12-Bit SAR ADC in 22nm FDSOI Utilizing an Inverter-Based Comparator Architecture
6个月前
已完结
A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA
6个月前
已完结
A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization
9个月前
已完结
Analysis and Design of Low-Noise Low-Offset Comparators for High-Performance ADC
9个月前
已完结
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