Lv63
2820 积分 2023-04-14 加入
Digital-to-Time Converter and Its Application to Fractional-N Frequency Synthesis: Circuits from a Systems Prospective
3个月前
已完结
Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation
10个月前
已完结
A High-Speed and Fully Symmetric Time-to-Digital Converter with Picosecond Resolution
11个月前
已完结
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS
11个月前
已完结
A TDC With Integrated Snapshot Circuit and Calibration in 28nm CMOS
11个月前
已完结
4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL
1年前
已完结
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
1年前
已完结
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
1年前
已完结
A Fractional-N DTC-based ADPLL using path-select multi-delay line TDC and true fractional division technique
1年前
已完结
8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
1年前
已完结
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