Lv7
4455 积分 2020-08-22 加入
A 13b 2GS/s Time-Domain Pipelined ADC with Split-CDAC Ping-Pong Residue Transfer and PVT-Robust Self-Tracked Time Amplifier
1天前
待确认
A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS
5天前
已完结
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment
5天前
已完结
CrossKV: Accelerating Large Language Model Inference via Cross-Stage Dynamic Co-Optimization for KV Cache
8天前
已完结
A 9b 3-7.5GHz 2.53LSB-INL High Linearity Phase Interpolator with CMOS-Signal-Targeted Calibration in 65nm for High-Speed Data Links
10天前
已完结
A 1.25-GS/s 12-bit inter-stage gain calibration-free pipelined ADC with gain-enhanced and current-biased ring amplifiers
15天前
已完结
A 200-MS/s 12-b Synchronous SAR ADC with Low Noise Comparator in 28-nm CMOS
15天前
已完结
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS
17天前
已完结
All-Digital Background Calibration of a Pipelined-SAR ADC Using the “Split ADC” Architecture
17天前
已完结
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
17天前
已完结
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