Lv72
4435 积分 2020-08-22 加入
A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction
7小时前
待确认
A Wideband Input Buffer Based on AC-Coupled Flipped Source Follower Using Auxiliary Operational Amplifiers for 8-GS/s ADCs
1天前
待确认
A Single-Channel 14B 3GS/s Pipelined ADC in 28nm Technology
5天前
已完结
A Single-Channel 14B 3GS/s Pipelined ADC in 28nm Technology
7天前
已完结
A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC
8天前
已完结
Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration
9天前
已完结
A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs
9天前
已完结
An Efficient Technique for Pipelined SAR ADC with Dynamic Bulk Biasing Design
10天前
已完结
Bulk-Input VCO-Based Sigma-Delta ADCs with Enhanced Linearity in 28-nm FD-SOI CMOS
10天前
已完结
A 0.2-V 10-bit 5-kHz SAR ADC with Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator
10天前
已完结
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