Lv71
4690 积分 2020-08-22 加入
A 12b 3 GS/s Passive T/H Assisted Time-Interleaved Pipelined SAR ADC with Metastability Reduction Technique and Dynamic-Bias RA
6小时前
已完结
A 55-nm 10-GS/s 6-b Time-Interleaved SAR ADC With Bandwidth Boosting Techniques
5天前
已完结
A genetic algorithm-based capacitor mismatch calibration scheme for SAR ADCs
6天前
已完结
16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology
9天前
已完结
An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS
13天前
已完结
26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS
13天前
已完结
A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization
14天前
已完结
A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm2 and 500 mW in 40 nm Digital CMOS
14天前
已完结
A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier
14天前
已完结
An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier
14天前
已完结
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