Lv71
5009 积分 2020-08-22 加入
A 12-bit 1.25-GS/s 164.3-dB FoMs Pipelined SAR ADC Featuring a Split SAR Stage With Input-Independent Transfer Switch
11天前
已完结
A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion
15天前
已完结
A 12-bit 1.25 GS/s Ping-Pong pipelined-SAR ADC employing a gain-enhanced ring amplifier with Miller negative capacitance
27天前
已完结
A Single-Channel 3.1GS/s 45dB SNDR Pipelined ADC using Amplify-and-Select Structure in 28nm CMOS
1个月前
已完结
A 12-bit 78.8-dB SFDR 625-MS/s Two-step Pipelined-SAR ADC With Self-Adaptive Common-Mode Capacitor Multiplier
2个月前
已完结
An SAR-Assisted Noise-Shaping Pipeline ADC With Gain-Boosted Cascoded Floating Inverter Amplifier
2个月前
已完结
A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction
2个月前
已完结
A 61.4 Gb/s/mm Wireline Transceiver Using a 7 bit-Over-8 Lane Symmetric Correlated Coding for High-Density Interconnects
2个月前
已完结
A Single Channel Two-Stage 12b 500MS/s Pipelined-SAR ADC with Reset-independent Asynchronous SAR Logic and Differential Flipped Voltage Follower Based Two-Stage Open-Loop Dynamic Amplifier
2个月前
已完结
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET
3个月前
已完结
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