Lv71
4900 积分 2020-08-22 加入
A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS
19天前
已完结
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
19天前
已完结
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS
19天前
已完结
A low-voltage input buffer with linearity-enhancement scheme for a 500MS/s Pipelined-SAR ADC achieving SFDR 79dBc
22天前
已完结
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
1个月前
已完结
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs
1个月前
已完结
Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC
1个月前
已完结
An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier
1个月前
已完结
A 13-GS/s 9-bit Time-Interleaved Pipelined-SAR ADC With Common-Mode Regulated Floating-Inverter-Amplifier and Rapid-Tracking Bootstrapped Switch
1个月前
已完结
An 8-bit 160-MS/s Charge Injection SAR ADC With Build-In Offset Calibration for Computing-in-Memory Macros
1个月前
已完结
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