Lv7
4829 积分 2020-08-22 加入
A 12-bit 78.8-dB SFDR 625-MS/s Two-step Pipelined-SAR ADC With Self-Adaptive Common-Mode Capacitor Multiplier
16天前
已完结
An SAR-Assisted Noise-Shaping Pipeline ADC With Gain-Boosted Cascoded Floating Inverter Amplifier
29天前
已完结
A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction
29天前
已完结
A 61.4 Gb/s/mm Wireline Transceiver Using a 7 bit-Over-8 Lane Symmetric Correlated Coding for High-Density Interconnects
30天前
已完结
A Single Channel Two-Stage 12b 500MS/s Pipelined-SAR ADC with Reset-independent Asynchronous SAR Logic and Differential Flipped Voltage Follower Based Two-Stage Open-Loop Dynamic Amplifier
1个月前
已完结
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET
1个月前
已完结
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps
1个月前
已完结
A 12-bit 10 GS/s Pre-Sampling Pipelined ADC With Split-Capacitor-Based Parasitic Compensation Technique
1个月前
已完结
A 16-bit 1-MS/s SAR ADC With Redundant Split Capacitor Array and Parasitic Capacitance Calibration
1个月前
已完结
A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC
2个月前
已完结
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