Lv719
5000 积分 2020-12-07 加入
A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR
3天前
已完结
A 28nm Multimode Multiband RF Transceiver with Harmonic-Rejection TX and Spur-Avoidance RX Supporting LTE Cat1bis
4天前
已完结
A Compact Ultra-High-Linearity 7-to-20 GHz Passive Mixer Achieving up to 37 dBm IIP3 and 25.1 dBm IP1dB in 45nm CMOS SOI
4天前
已完结
The Design of An LDO Regulator [The Analog Mind]
6天前
已完结
A 11.3–16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS
1个月前
已完结
A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS
1个月前
已完结
An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique
1个月前
已完结
A 4-port inductor based compact dual-core VCO with improved phase noise performance
1个月前
已完结
An 80-GHz Phase-Locked Loop for MillimeterWave Application in 40-nm CMOS
1个月前
已完结
Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-$\mu$s Locking Time
1个月前
已完结
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