Lv724
4900 积分 2020-12-07 加入
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
12天前
已完结
A Low-Jitter Fractional-N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology
12天前
已完结
A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
12天前
已完结
A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
12天前
已完结
A Fractional-$N$ Sampling PLL With a Merged Constant-Slope DTC and Sampling PD
17天前
已完结
A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique
17天前
已完结
An Alternative Analysis of Noise Folding in Fractional-N Synthesizers
17天前
已完结
A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving $-$46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal
22天前
已完结
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs
26天前
已完结
A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range
27天前
已完结
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