Lv41
660 积分 2024-07-11 加入
True random calibration method and application of tapped delay line-TDC with spontaneous parametric down-conversion system
5小时前
待确认
Heterogeneous Tapped Delay-Line Time-to-Digital Converter on Artix-7 FPGA
5小时前
待确认
A 64-channel precision Time-to-Digital Converter with average 4.77 ps RMS implemented in a 28 nm FPGA
5小时前
待确认
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
5小时前
待确认
A low-dead-time, sub-100 ps 144-channel TDC based on Kintex Ultrascale FPGA
5小时前
求助中
A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA
1个月前
已完结
A Sub-Nanosecond Time Interval Detection System Using FPGA Embedded I/O Resources
1个月前
已完结
A High-Resolution (<formula formulatype="inline"> <tex Notation="TeX">${&lt; 10}~{\rm ps}$</tex></formula> RMS) 48-Channel Time-to-Digital Converter (TDC) Implemented in a Field Programmable Gate Array (FPGA)
1个月前
已完结
The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay
1个月前
已完结
Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution
1个月前
已完结
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