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24 积分 2025-09-24 加入
PAR2DF: Power and Area Efficient Retiming 2D FIR Filter Architecture Using Optimized Multipliers and Adders
22天前
已完结
A 14-b 65.3-dB SNDR 200-MS/s Coarse-fine SAR ADC with Rail-to-Rail Input Common Mode Range in 28-nm CMOS
22天前
已完结
A 18-bit 1-MS/s fully-differential SAR ADC with digital calibration achieving 96.1 dB SNDR
1个月前
已完结
A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC
1个月前
已关闭
A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications
1个月前
已完结
A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems
1个月前
已完结
High-resolution calibrated successive-approximation-register analog-to-digital converter
1个月前
已关闭
A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration
1个月前
已完结
A low power SAR ADC with fine–tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS
2个月前
已关闭
A Generic Foreground Calibration Algorithm For ADCs with Nonlinear Impairments
3个月前
已完结
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