Lv41
570 积分 2020-04-13 加入
Design of Low Power and High Speed XOR/XNOR Circuit using 90 nm CMOS Technology
9小时前
已完结
Analysis of accumulated timing-jitter in the time domain
25天前
已完结
A Bandwidth-Tracking Self-Biased 5-to-2800 MHz Low-Jitter Clock Generator in 55nm CMOS
1个月前
已完结
A 10 MHz to 3.2 GHz Differential Current Starved Inverter-Based Self-Biased Adaptive Bandwidth PLL in 65nm CMOS
1个月前
已完结
A low-jitter self-biased phase-locked loop for SerDes
1个月前
已完结
A low jitter self-calibration PLL for 10Gbps SoC transmission links application
1个月前
已完结
A Low Power Frequency Synthesizer with Dual-Path Architecture
1个月前
已完结
A 65nm CMOS low-power, low-voltage bandgap reference with using self-biased composite cascode opamp
7个月前
已完结
A 65nm CMOS low-power, low-voltage bandgap reference with using self-biased composite cascode opamp
7个月前
已关闭
High Accuracy Self-Biasing Cascode Current Mirror
7个月前
已完结
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