钝化
材料科学
薄膜晶体管
光电子学
氧化物薄膜晶体管
氧化物
无定形固体
阈值电压
晶体管
纳米技术
图层(电子)
电气工程
电压
化学
冶金
结晶学
工程类
作者
Yuhao Shi,Yu‐Shien Shiah,Kihyung Sim,Masato Sasase,Junghwan Kim,Hideo Hosono
摘要
Maintaining gate bias stability under negative bias stress (NBS) and positive bias stress (PBS) is a long-standing issue in amorphous oxide semiconductor thin-film transistors (TFTs). The passivation of the channel layer is crucial for improving device stability. We show that amorphous gallium oxide, which possesses appropriate energy levels (lower electron affinity and higher ionization potential) for indium–tin–zinc oxide (ITZO) TFTs, can be etched selectively by tetramethyl ammonium hydroxide-containing developers that enable self-alignment passivation, such as easy contact hole formation during the drain and source lithography processes. The self-aligned passivation process led to a-ITZO TFTs with high mobility (>50 cm2 V−1 s−1) and low subthreshold swing (<90 mV/dec). The threshold voltage shifts under NBS and PBS using a bias gate voltage of ±20 V for 1 h were −0.09 and 0.15 V, respectively. This passivation can obviate the need for the conventional CVD-derived passivation process by utilizing the DC sputtering of gallium oxide, which may reduce hydrogen issues.
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