Efficient hardware realization and high radix implementation of modular multi exponential techniques for public key cryptography

Modular multi exponentiation (MME) is a critical operation in most of the public-key cryptosystems and verification functions. Two novel algorithms: HRMME and SFWHRMME, are proposed to evaluate the MME efficiently. The evaluation process of the proposed algorithm has an inbuilt confusion mechanism, which increases the security level. The side-channel attacks and timing attacks are counteracted by algorithmic means instead of using only hardware measures. The high-radix implementation is efficiently reducing the required number of clock cycles. The performance of the proposed algorithms is analyzed in terms of power, throughput and energy. The experimental results show that the proposed techniques HRMME and SFWHRMME increase the throughput in the order of 23.55% and 23.67%, respectively and consume less power in the order of 21.78% and 21.88%. Xilinx Vivado 21.2 on Virtex-7 evaluation boards and ICARUS Verilog simulation & synthesis tools are used for FPGA for hardware realization. The hardware compatibility of proposed algorithms has also been checked using Cadence for ASIC.