中间层
材料科学
电容器
薄脆饼
去耦电容器
化学机械平面化
炸薯条
光电子学
互连
电感
终端(电信)
蚀刻(微加工)
电子工程
电气工程
计算机科学
图层(电子)
纳米技术
工程类
电压
计算机网络
电信
作者
Yoshiaki Satake,Tatsuya Funaki,Kyosuke Kobinata,Hitoshi Matsuno,Seiji Hidaka,Shunsuke Abe,Hiroyuki Ito,Chin Tsai Hsiao,Sheng Yi Li,Young-Suk Kim,Takayuki Ohba
标识
DOI:10.1109/ectc51906.2022.00053
摘要
A multi-terminal Si capacitor with low equivalent series inductance (ESL) for power delivery systems in 2.5D/3D applications was demonstrated. The shortest parallel interconnects with a length of 20 μm from a power delivery network of RDL to the capacitor were successfully fabricated, in a 3D functional interposer, a Si capacitor is connected through Cu pads and through silicon vias (TSVs) formed by a bumpless Chip-on-Wafer (COW) process. By optimizing the capacitor direct-stack process with an adhesive curing profile and a TSV profile hy dry etching, 700 TSV connections with no open failures were achieved.
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