Thermal management of lateral GaN power devices

This article investigates several thermal management techniques for GaN transistors with a Wafer-Level Packaging (WLP): advanced techniques are used to mount them on Direct-Bonded Copper (DBC) ceramic substrates, with the heat removed either through the topside of the die (as recommended by the manufacturer), or through the backside. The thermal resistance of the assembly is measured in the different configurations, for different die thicknesses. The paper describes the manufacturing process and the thermal simulation and experimental results will be shown.