PCI Express
抖动
CMOS芯片
计算机科学
电子工程
电气工程
计算机硬件
工程类
电信
现场可编程门阵列
作者
Moon-Chul Choi,Sang‐Hee Lee,Seungha Roh,Kwang-Ho Lee,Jonghyun Oh,Sung Woo Kim,Kwandong Kim,Woo-Seok Choi,Jaeha Kim,Deog‐Kyoon Jeong
出处
期刊:IEEE Transactions on Circuits and Systems Ii-express Briefs
[Institute of Electrical and Electronics Engineers]
日期:2022-06-01
卷期号:69 (6): 2677-2681
被引量:4
标识
DOI:10.1109/tcsii.2022.3153396
摘要
This brief presents a 2.5 – 32 Gb/s Gen 5-PCIe receiver with a multi-rate clock and data recovery (CDR) engine and a hybrid decision feedback equalizer (DFE). The receiver for the PCIe requires wide-range operation and compensation for high insertion loss. The proposed multi-rate CDR engine enables the receiver to operate with multi-rate clocking schemes according to the data rates, which does not need any additional high-speed analog circuits normally used for wide-range operation. In addition, the hybrid DFE architecture not only meets the DFE feedback timing constraint and but also reduces the equalization power. By using clock gating, the receiver can save power when operating at lower generations such as Gen 1, 2, 3, and 4. The prototype chip is fabricated in a 40-nm CMOS technology and occupies an active area of 0.14 mm 2 . The receiver achieves BER less than 10 −12 with various PCIe channels, satisfying PCIe jitter tolerance masks. It consumes 62.7 mW at 32 Gb/s, compensating for 27.5-dB inserting loss, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.07 pJ/b/dB is achieved.
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