Endurance Improvement of Si FeFET by a Fully CMOS-Compatible Process: Insertion of HfO x at Hf0.5Zr0.5O2/SiO x Interface to Suppress Oxygen Vacancy Generation

This work investigates the endurance characteristic of Si FeFET with Hf0.5Zr0.5O2 ferroelectric. A fully CMOS-compatible method is shown to improve endurance: insertion of the thin HfOx layer (~2–5Å) at the Hf0.5Zr0.5O2/SiOx interface. The ab initio calculations prove that the HfOx insertion can increase the formation energies of oxygen vacancies and suppress their generation in the gate stacks and, consequently, improve the endurance. This method paves a possible path to improve the endurance of Si FeFET.