倒装芯片
芯片级封装
包对包
四平无引线包
引线键合
成套系统
模具(集成电路)
互连
集成电路封装
热铜柱凸点
小型化
炸薯条
电子包装
包装工程
基质(水族馆)
材料科学
计算机科学
电子工程
薄脆饼
电气工程
工程类
光电子学
图层(电子)
机械工程
电信
纳米技术
晶片切割
胶粘剂
海洋学
地质学
作者
Raj Pendse,BS Choi,Baker Kim,K.M. Kim,Y.C. Kim,Kenneth Lee,Susan Park,DW Yang,Lily Zhao,Tom Gregorich,Pat Holmes,Ed Reyes
标识
DOI:10.1109/ectc.2007.373982
摘要
A new chip scale package is developed for use in high end cellular handsets and mobile products. The package houses a Baseband device, a pre-packaged Memory device and an Analog device in a 3-high stacked Package-in-Package (PiP) configuration wherein the base band die is attached to a 4-layer 1-2-1 Build-up laminate substrate using flip chip interconnection and the Memory package and Analog die are interconnected to each other as well as to the substrate using wire bonding. The package represents the ultimate in integration, wiring density, high performance and miniaturization. The development of the package was accomplished through close co-working of multidisciplinary teams comprising packaging, design and device architecture. The paper describes the challenges in the development of the individual packaging technologies such as bumped wafer thinning, thin die flip chip attach and underfilling, low loop wire bonding and the integration of those technologies, such as flip chip and wire bonding on the same substrate, underfill and overmolding, and chip-package interactions in the form of parametric shifts in sensitive analog circuitry on the die. The assembly process, reliability and failure modes observed are described in detail including the eventual qualification of the package and its introduction into volume production.
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