材料科学
原子层沉积
电介质
化学气相沉积
深能级瞬态光谱
高-κ电介质
栅极电介质
图层(电子)
光电子学
晶体管
纳米技术
硅
电压
电气工程
工程类
作者
Kexin Deng,Xinhua Wang,Sen Huang,Qimeng Jiang,Haibo Yin,Jie Fan,Guanjun Jing,Yingjie Wang,Tiantian Luan,Wei Ke,Yingkui Zheng,Jingyuan Shi,Xinyu Liu
标识
DOI:10.1016/j.apsusc.2022.154937
摘要
• A sharp LPCVD-SiN x /GaN interface is obtained by the PEALD-SiO x N y interfacial layer in contrast to a rough interface in the sample without the interfacial layer. • The conduction band offset (ΔE C ) between the LPCVD-SiN x dielectric and GaN increases from 2.67 to 3.77 eV by the PEALD-SiO x N y interfacial layer. • Isothermal capture transient and constant-capacitance deep-level transient spectroscopy (CC-DLTS) measurements prove the deep interface states and the electron-trapping by the bulk states in LPCVD-SiN x dielectric are effectively blocked by the PEALD-SiO x N y interfacial layer at high gate bias. A 3nm-thick SiO x N y grown by plasma-enhanced atomic layer deposition (PEALD) at 500 o C, is utilized as the interfacial layer to suppress the deep interface states and dielectric trapping in SiN x /GaN metal-insulator-semiconductor (MIS) structures. It is capable of protecting the GaN surface from decomposing during the growth of SiN x dielectric by low-pressure chemical vapor deposition (LPCVD) at a relatively high temperature of 780 o C. The SiN x /GaN interface with the PEALD-SiO x N y interfacial layer features a sharp interface, a remarkably reduced threshold voltage hysteresis (Δ V TH ) as well as suppressed interface state density. The conduction band offset (ΔE C ) between the LPCVD-SiN x dielectric and GaN increases from 2.67 to 3.77 eV by the PEALD-SiO x N y interfacial layer. It is verified by isothermal capture transient as well as constant-capacitance deep-level transient spectroscopy (CC-DLTS) measurements that, the electron-trapping by the bulk states of E C -E T ∼ 1.1 eV in the LPCVD-SiN x dielectric and the deep interface states, can be effectively blocked by the PEALD-SiO x N y interfacial layer at high gate bias. The LPCVD-SiN x / PEALD-SiO x N y bilayer could be a compelling gate dielectric for III-nitride MIS high-electron-mobility transistors (HEMTs).
科研通智能强力驱动
Strongly Powered by AbleSci AI