A layout-to-simulation approach for thermal design of IC

After decades of development along with the Moore's Law, integrated circuits (IC) have become smaller and smaller in the feature size, thereby higher and higher in the integration degree. With the increment of the power density and the introduction of low thermal conductivity materials, the heat dissipation in integrated circuits has become the most challenge issue. Co-design of thermal and electrical performances is highly in demands to solve this issue. However, current EDA tools for the electrical design and the thermal simulation are not well correlated, and a lot of efforts have to be put on the physical modelling, especially for the three-dimensional (3D) simulation of temperature distribution inside the ICs. This paper introduces a layout-to-simulation approach to bridge the layout design and the full-scale finite element method. This design starts directly from the layout of the chip by extracting the feature structure from the layout file (GDS2), modelling the 3D geometrical structure, assigning the material and physical field/boundry parameters, and finally running the simulation after meshing and configuring the solver. The test case has a layout with size of 2 mm×2 mm with 6 different layers to realize the heater, temperature sensors and microfluidic cooling channels. We mainly study the 6-layer heater. Temperature distribution inside the chip is obtained after the finite element simulation to fasten the co-design procedure. This work presents a promising strategy for co-designs of electrical and thermal performance of the IC.