单片微波集成电路
放大器
高电子迁移率晶体管
功率增加效率
功率带宽
电气工程
射频功率放大器
线性放大器
直接耦合放大器
材料科学
功率增益
电子工程
工程类
运算放大器
晶体管
CMOS芯片
电压
作者
Wonseob Lim,Hwiseob Lee,Hyunuk Kang,Wooseok Lee,Kang‐Yoon Lee,Keum Cheol Hwang,Youngoo Yang,Cheon‐Seok Park
标识
DOI:10.5573/jsts.2016.16.3.339
摘要
This paper presents a two-stage power amplifier MMIC using a 0.4 μm GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of 2.0×1.9 mm² and was mounted on a 4×4 QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.
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