抵抗
材料科学
CMOS芯片
光电子学
过程(计算)
蚀刻(微加工)
纳米技术
薄膜
工程物理
计算机科学
工程类
图层(电子)
操作系统
作者
Brian Martin,Graham G. Arthur,Charles L. Brown
标识
DOI:10.1016/s0167-9317(98)00029-x
摘要
Difficulties in controlling size of contact holes in a sub-half-micron CMOS process using planarisation by resist etch back are discussed. In particular, the limitations of using top anti-reflective coatings to overcome thin film effects on transparent substrates are calculated by simulation. Use of bottom anti-reflective coatings to improve uniformity are described through practical results.
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