中间层
成套系统
三维集成电路
材料科学
通过硅通孔
光电子学
硅
集成电路封装
电子工程
嵌入式系统
计算机科学
电气工程
集成电路
炸薯条
工程类
纳米技术
蚀刻(微加工)
图层(电子)
作者
John H. Lau,Heng-Chieh Chien,Ray Tain
标识
DOI:10.1115/ipack2011-52204
摘要
A low-cost (with bare chips), high cooling ability and very low pressure drop 3D IC integration system-in-package (SiP) is designed and described. This system consists of a silicon interposer with through-silicon vias (TSV) and embedded fluidic microchannels, which carries all the Moore’s law chips and optical devices on its top and bottom surfaces. TSVs in the Moore’s law chips are optional but should be avoided. This novel structural design offers potential solutions for high-power, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost 3D IC SiP applications.
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