Focus spot monitoring: design of an automatable detection, classification, and impact analysis pipeline

Integrated Circuit (IC) fabrication requires performing a long sequence of complex process steps. Among them, photolithography patterning plays the most important role to define the dimensions, doping regions, and intercon nections for each device. With the advancement of lithographic processing, minimum feature sizes continue to shrink, and the devices become denser. At the same time, the specifications for overlay accuracy, wafer critical dimension uniformity, and acceptable focus deviations also become tighter. Hence, even nanometer-sized defects on wafer substrates can ha ve a crucial impact on the quality of the lithographic exposures and limit the performance of such devices. Detection and elimination of such surface defects ("focus spots") at the early stage of processing have been of primary concern to prevent the loss in manufacturing productivity and significant product yield degradation. In this paper, we present a focus spot monitoring framework to detect focus spots and chuck spots accurately by using wafer leveling data. We discuss different strategies how to detect focus spots, how to classify them, and how to monitor and correct them effectively. We evaluate existing focus spot monitoring solutions and how to improve upon them. Altogether, a stable, reliable focus spot monitoring solution is described for optimal focus corrections and rework decisions.