电网设计
去耦电容器
炸薯条
电容器
现场可编程门阵列
芯片上的系统
嵌入式系统
解耦(概率)
计算机科学
电气工程
工程类
电子工程
电压
控制工程
作者
Md Obaidul Hossen,Ankit Kaul,Eriko Nurvitadhi,Mondira Pant,Ravi Gutala,Aravind Dasu,Muhannad S. Bakir
出处
期刊:IEEE Transactions on Components, Packaging and Manufacturing Technology
[Institute of Electrical and Electronics Engineers]
日期:2022-11-01
卷期号:12 (11): 1824-1831
被引量:2
标识
DOI:10.1109/tcpmt.2022.3223687
摘要
In this article, we investigate the impact of power delivery network (PDN) in bridge-chip-based 2.5/3-D heterogeneous integration platforms. The focus of the article is bridge-chip-based central processing unit (CPU)-field-programmable gate array (FPGA) and FPGA-stacked memory integration technologies. While bridge-chip-based interconnect platforms present PDN challenges, depending on the power map, including a PDN in the bridge-chip can help reduce the impact significantly. We perform three case studies: 1) inclusion of ground network in the bridge-chip; 2) inclusion of power and ground network in the bridge-chip; and 3) inclusion of metal-insulator-metal (MIM) decoupling capacitors in the bridge-chip. Inclusion of both power and ground network can reduce DC IR drop by ~20% for a CPU-FPGA integration case study and by ~40% for an FPGA-stacked memory configuration. Our $L (di/dt)$ noise analysis shows that if we include decoupling capacitors in the bridge-chip, we can significantly reduce the high-frequency ripple in the power supply. We also perform a design space exploration for power delivery with the following parameters: 1) resistance of the PDN in the bridge-chip; 2) decoupling capacitor density in the bridge-chip; and 3) overlap region between a bridge-chip and active dice.
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