An Efficient and Accurate DTCO Simulation Framework for Reliability and Variability-Aware Explorations of FinFETs, Nanosheets, and Beyond

Design-Technology Co-Optimization (DTCO) emerged as pivotal driver in shaping the state-of-the-art nodes and will gain evermore importance for future technologies. This becomes most evident with the advent of complementary FETs (CFET), a technology which thrives on intricately engineered design and technology to achieve substantial boosts for both logic and memory applications. Practical DTCO implementations are realized by combination of TCAD and SPICE to achieve studies with quick turnaround times (TAT) and for seamless integration with the standard EDA design flow. Here, such a TCAD-to-SPICE DTCO flow is outlined and its application for reliability and variability-aware SRAM and RO is demonstrated.