32nm CMOS Analog Circuit Implementation of STDP for SNNs

Spiking Neural Network is a network that operates with neurons that generate voltage or current spikes and are connected by synapses. Spike Time Dependent Plasticity (STDP) is a learning rule which governs how strong or weak the connections between two neurons will be based on temporal information of spike activity of two connected neurons. We propose a 32nm analog CMOS implementation of STDP based synapse in this work. Simulation results demonstrate that the circuit effectively emulates the behavior of STDP. The proposed circuit can be used as a synapse in the construction of a complete SNN architecture.