薄膜晶体管
材料科学
阈值电压
栅极电介质
无定形固体
电介质
栅氧化层
光电子学
溅射
镓
压力(语言学)
基质(水族馆)
晶体管
薄膜
图层(电子)
复合材料
冶金
电气工程
电压
纳米技术
化学
哲学
有机化学
工程类
地质学
海洋学
语言学
作者
Sung Haeng Cho,Min Ki Ryu,Hee‐Ok Kim,Oh‐Min Kwon,Eun-Sook Park,Yong-Suk Roh,Chi‐Sun Hwang,Sang‐Hee Ko Park
标识
DOI:10.1002/pssa.201431062
摘要
We report the simultaneous improvements of the threshold voltage (Vth) stabilities under the prolonged positive gate bias stress (PBS) and negative gate bias under illumination stress (NBIS) by employing the gate dielectric/channel interface engineering in the bottom-gate, DC-sputtered amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFT). In the interfacial region, a-IGZO is grown under the low oxygen partial pressure () condition to minimize the damage from highly energetic oxygen anion bombardment into the substrate during sputtering. Meanwhile, high is employed during the bulk growth of active film to reduce the oxygen vacancy (VO) related defects in a-IGZO, which is known to be a main cause for the degradation of the electrical properties of TFT under NBIS. Owing to the lower damage of the gate dielectric by interface engineering during sputter deposition, the charge trapping or injection probability into the gate dielectric is diminished. Consequently, Vth instabilities due to both the electron trapping under PBS and the trapping of positively charged species under NBIS are alleviated simultaneously.
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