材料科学
电介质
光电子学
晶体管
栅极电介质
俘获
绝缘体(电)
磁滞
场效应晶体管
导带
高-κ电介质
凝聚态物理
电压
电气工程
电子
物理
生态学
量子力学
生物
工程类
作者
Giheon Kim,Dang Xuan Dang,Hamza Zad Gul,Hyunjin Ji,Eun Kyu Kim,Seong Chu Lim
出处
期刊:Nanotechnology
[IOP Publishing]
日期:2023-10-07
卷期号:35 (3): 035702-035702
被引量:2
标识
DOI:10.1088/1361-6528/ad0126
摘要
Two-dimensional material-based field-effect transistors are promising for future use in electronic and optoelectronic applications. However, trap states existing in the transistors are known to hinder device performance. They capture/release carriers in the channel and lead to hysteresis in the transfer characteristics. In this work, we fabricated MoTe2field-effect transistors on two different gate dielectrics, SiO2and h-BN, and investigated temperature-dependent charge trapping behavior on the hysteresis in their transfer curves. We observed that devices with SiO2back-gate dielectric are affected by both SiO2insulator traps and MoTe2intrinsic bulk traps, with the latter becoming prominent at temperatures above 310 K. Conversely, devices with h-BN back-gate dielectric, which host a negligible number of insulator traps, primarily exhibit MoTe2bulk traps at high temperatures, enabling us to estimate the trap energy level at 389 meV below the conduction band edge. A similar energy level of 396 meV below the conduction band edge was observed from the emission current transient measurement. From a previous computational study, we expect these trap states to be the tellurium vacancy. Our results suggest that charge traps in MoTe2field-effect transistors can be reduced by careful selection of gate insulators, thus providing guidelines for device fabrication.
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