触发器
示意图
节奏
感测放大器
功率(物理)
放大器
电子工程
计算机科学
波形
电气工程
电压
工程类
CMOS芯片
物理
量子力学
作者
Sushmita Kumari,Baljit Kaur,D. Vaithiyanathan,Alok Kumar Mishra
标识
DOI:10.1109/gcat55367.2022.9972071
摘要
In this paper, sense amplifier based flip flop (SAFF) with different latch designs is implemented and analyzed with respect to minimum voltage supply, delay and power. The conventional SAFF along with Power PC Master Slave flip flop (MSFF) and Pulse triggered flip flop (PTFF) are also discussed. In the result section, the output waveform and parametric analysis of all the SAFFs are implemented and results of comparison of each schematic are also discussed. The schematic of all the flip flops are designed using gdpk90nm and simulated using cadence tool.
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