Study of the protrusion of through-silicon vias in dual annealing-CMP processes for 3D integration

Abstract The technology of through-silicon via (TSV) is extensively employed for achieving dense 3D integration. TSV facilitates the electrical interconnection of various layers of integrated circuits in a vertical orientation, thereby allowing for the creation of sophisticated and space-efficient systems that incorporate diverse functionalities. This work reports TSV fabrication with dual annealing-CMP processes to explore the influence of annealing and CMP processes on the evolution of TSV-Cu microstructures and protrusions. The results show that the dual CMP process can effectively reduce protrusion at high temperatures. The Cu protrusion height increased as both the annealing temperature and duration increased, which was consistent with the high-temperature annealing results, whereas a random phenomenon occurred under 250 °C annealing. A phase field model related to the TSV grain size was established to quantitatively explore the grain morphology distribution and thermal-mechanical behavior. The results show that the strain in copper is nonuniform and that the degree of plastic deformation for each grain is closely related to its distribution. The quantity of grains within the TSV is the most important factor for protrusion. As the average grain size increases, the prominence of copper grain protrusions within TSV intensifies, and the anisotropy of the Cu grains becomes more pronounced. The thermal-mechanical behavior strongly depends on the grain orientation near the top of the TSV, which can cause TSV protrusion irregularities. This work may provide more opportunities to design high-performance TSV preparation methods from the viewpoint of the dual CMP process.