The Critical Role of Dielectric Trench Etch in Enhancing Cu/low-k Dielectric Reliability for Advanced CMOS Technologies

In this work, we focused on the via-first approach and studied the impacts of trench etch on the electrical reliability of copper interconnects in terms of electro migration (EM), stress migration (SM), time dependent dielectric breakdown (TDDB) and chip package interaction (CPI). The huge micro-trench formed during trench etch could lead to the inter-layer voltage break-down, thus triggering CPI failure. Polymer and bombardment have been well managed in trench etch to solve this issue without degrading TDDB performance. Besides, post-etch treatment (PET) has been proven effective and critical in enhancing EM, SM and TDDB performance but it direct extension to M1 etch need reassess for the sake of trench etch recipe and substrate difference.