Design of Low-Power High-Speed Double-Tail Dynamic Comparator Based on Charge-Steering Concept

Abstract In this thesis, a low-power dissipation high-speed double-tail dynamic comparator is designed. Based on the principles of charge-steering, a clock charge pump is used at the tail of the latch stage to replace the clock current source, which reduce the output swing and kick-back noise of the comparator. Meanwhile, digital logic is added to the pre-amplification stage to eliminate quiescent current and further reduce power consumption. Based on the SMIC 28nm CMOS process, the proposed comparator is simulated and verified. The results show that under the condition of 0.9V supply voltage and 1MHz sampling frequency, the power dissipation is 5.4μW, the delay is 245ps, and the offset voltage is 6.9mV. Compared with a high-speed comparator, under the premise of achieving the same performance, the power consumption is reduced by 69%.