Optimization of 3-D IC Routing Based on Thermal Equalization Analysis

Three-dimensional integrated circuits (3D ICs) offer performance advantages due to their reduced wiring overcomes the drawbacks of 2D IC and a vital structure called through-silicon via (TSV) is used to connect the adjacent layers vertically. However, the 3D structure will inevitably lead to thermal issues, and poor routing management in 3D ICs will lead to the increase of thermal stress in 3D IC chips and the deterioration of system stability. In this paper, based on thermal equalization, the chip-silicon interposer-printed circuit board (PCB) assembly structure is simulated and analyzed combined with layout design to investigate the impact of layout, solder ball selection, and TSV layout on the routing of 3D IC layout. The simulation results demonstrate our routing optimization method achieves optimized thermal stress, less large local deformation, reduced temperature, and higher system stability.