Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs

Abstract In this paper we present an extended analysis of thsse impact of SiGe p-epi source/drain engineering on sub-20 nm gate length p-FinFETs performance for the N7 technology node. Different Ge concentrations and profiles (graded versus non-graded) are evaluated making use of properly calibrated drift-diffusion TCAD simulations. Calibration of simulations is based on advanced metrology and on Monte-Carlo simulations such that the resulting simulated ID-VG (in LIN and SAT regimes) matches the one measured on device. The calibrated TCAD simulator is then used to understand the limited performances of the device and to propose new source/drain epi architectures with graded and increased Ge content. A new p-FinFET design is fabricated and tested, confirming a boost in ON-current and a reduction of the parasitic resistance. Prospective TCAD work is also presented suggesting possible future improvements on p-epi source/drain and on local interconnect contacts.