Stress investigations in 3D-integrated silicon microstructures

With the anticipated slow-down of Moore's Law in the near future, three-dimensional (3D) packaging of microelectronic structures would enable to further increase the integration density required to meet the forecasted demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile communicatoin and other emerging technologies. Through-silicon vias (TSVs) are a pathway to provide electrical connections for signaling and power-delivery through 3D-stacked silicon (Si) microstructures. TSVs and related structures such as, e.g., interconnects and redistribution lines, however, induce stress in their proximity, namely upon electrochemical deposition and subsequent annealing, the latter due to the large mismatch in the coefficient of thermal expansion between Si and the TSV-filling materials used. Stress-induced crowding and relaxation of the Si lattice can cause a variety of issues ranging from active-device performance degradation, interfacial delamination or interconnect failures to cracking of the entire Si microstructures at stress hotspots upon assembly or operation. Employing a novel dual-shell Si interposer concept with both power delivery and signaling through TSVs, we aim at removing the heat dissipated from the active components sitting on top of one interposer shell through embedded liquid-cooling cavities, a strategy that generically enables true 3D stacking but may also induce additional stress. In the current paper, we reduce system complexity and first investigate, both experimentally and theoretically the TSV-induced stress profiles in one Si interposer half before introducing cooling cavities and sealing structures. After each processing step, the residual and non-thermal stress profile around the TSV is determined using a confocal Raman microscope with sub-micrometer spot-size acting as a local strain gauge. These measurements are conducted under ultra-silent conditions, revealing an unprecedented resolution of 0.01 cm-1, corresponding to approx. 4.3 MPa of stress in crystalline Si. A detailed comparison of measurements and finite element analysis (with the later taking into account geometry and material properties) is provided, revealing both a good qualitative and quantitative correlation between theory and experiment. We also show that athermal stress after copper deposition can be minimized during an annealing step.