探测器
物理
计算机科学
数据采集
CMOS芯片
调制(音乐)
电气工程
电子工程
计算机硬件
电信
光电子学
工程类
声学
操作系统
作者
Xiaoteng Zhao,Yong Chen,Lin Wang,Pui-In Mak,Franco Maloberti,Rui P. Martins
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2022-05-01
卷期号:57 (5): 1358-1371
被引量:8
标识
DOI:10.1109/jssc.2022.3140778
摘要
This article reports a half-rate single-loop bang-bang clock and data recovery (BBCDR) circuit without the need of reference and frequency detector (FD). Specifically, we propose a deliberate-current-mismatch charge-pump pair to enable fast and robust frequency acquisition without identifying the frequency error polarity. This technique eliminates the need for a complex high-speed data or clock path during the frequency acquisition, resulting in significant power savings. Prototyped in 28-nm CMOS, the BBCDR circuit automatically tracks a four-level pulse-amplitude modulation (PAM-4) input between 47.6 and 58.8 Gb/s. The core area is 0.056 mm 2 . Both the achieved energy efficiency (0.22–0.25 pJ/bit) and the acquisition speed [9.8 (Gb/s)/ $\mu \text{s}$ ] compare favorably with the state of the art.
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