Deterministic completion detection technique for asynchronous circuits using bundled data protocol

Because the presence of a global clock automates the timing control, the synchronous design approach is widely adopted by today’s electronic industry. As the need for fast and small electronic devices grows, it becomes increasingly difficult to construct circuits utilizing a single world clock. Asynchronous architecture, which substitutes the global clock with handshaking signals, is an alternative way to overcome the clock’s problems. In asynchronous circuits, encoding methods are combined with a completion detection scheme to regulate the process sequence. The dual-rail or bundled data protocol can construct a completion detecting circuit for an asynchronous system. The dual-rail protocol incorporates process completion information into the data itself; however, the enormous silicon area and time required to compute data validity may make it unworkable. On the other hand, the bundled data protocol uses handshaking signals to replace the global clock, and a worst-case delay is added to the control channel to assure data validity at the output, so it cannot make use of the asynchronous approach’s data-driven characteristic. On the other hand, a completion detecting circuit can replace the worst-case delay model by sending the acknowledge signal as soon as the data is legitimate. If the precise completion time is unknown, a deterministic completion detection technique for bundled data protocol might help with a better asynchronous design by solving the frequent issue of wasteful idle waiting associated with bundled data. This work proposes a general way to designing a deterministic completion detection system for asynchronous circuits utilizing the bundled data protocol. The processing time of an asynchronous barrel shifter is computed to show the optimized delay produced by employing the deterministic completion detection approach.