Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- $k$ Stacks

A novel voltage-ramp-stress (VRS) methodology is introduced for bias temperature instability testing of metal-gate/high- k (MG/HK) CMOS devices. Results from VRS are compared with the constant-voltage-stress procedure. It is demonstrated that the voltage and time dependence measured with both methods agree well with each other. These findings make the VRS test the preferred procedure for screening and process monitoring of MG/HK CMOS technologies because the test always yields measurable shifts and little knowledge about gate-stack details is required.