A 56-GHz Fractional-N PLL With 110-fs Jitter

A fractional- $N$ phase-locked loop (PLL) architecture incorporates a switched-current finite impulse response (FIR) filter to suppress the $\Delta \Sigma $ modulator ( $\Delta \Sigma \text{M}$ ) noise. Using a compact, low-power divide-by-8 circuit and realized in 28-nm CMOS technology, the PLL exhibits a phase noise of −98 dBc/Hz at 1-MHz offset in the fractional- $N$ mode while consuming 23 mW and occupying an active area of 0.1 mm 2.