德拉姆
极紫外光刻
PMOS逻辑
节点(物理)
计算机科学
存储单元
动态随机存取存储器
通用存储器
过程(计算)
晶体管
材料科学
嵌入式系统
电子工程
工程类
光电子学
电气工程
半导体存储器
内存管理
计算机硬件
操作系统
电压
结构工程
交错存储器
作者
Kanguk Kim,Youngwoo Son,Hoin Ryu,Byung-Hyun Lee,Jooncheol Kim,Hyunsu Shin,Joon‐Young Kang,Jihun Kim,Shinwoo Jeong,Kyo-Suk Chae,Dongkak Lee,Ilwoo Jung,Yongkwan Kim,Boyoung Song,Jeong‐Hoon Oh,Jungwoo Song,Seguen Park,Keumjoo Lee,Hyodong Ban,Jiyoung Kim
标识
DOI:10.23919/vlsitechnologyandcir57934.2023.10185314
摘要
As the most scaled memory solution at present, we for the first time developed and begun volume production of 14nm DRAM to extend the continuous shrink trend in semiconductor memory industry. In the new era of 14nm node DRAM and beyond, process integration and device performance are both essential due to the rapid increase of memory cell disturbance and resistance. To resolve the difficulty of process integration, five-layer EUV processes and L-CNT (Line-type storage node contact) scheme were devised, reducing the number of process steps by approximately 20%. To boost device performance, extremely shallow doping engineering played a pioneering role to advance the performance of PMOS transistor by 40% in terms of contact resistance. Our 14nm DRAM will provide the finest and most advanced solution for the next-generation DRAM platform–DDR5 and beyond.
科研通智能强力驱动
Strongly Powered by AbleSci AI